Bottome-up progression:
Number system -> Boolean algebra -> Boolean algebra using electrical switches -> Logic Gates -> addition (base of all calculation) -> subtraction -> combinational(NO FEEDBACK) without feedback, value change immediately (unstable) & sequential(FEEDBACK) feedback can make state(stable) -> memory, calculation without memory is not very useful -> Conditional Jump (Controlled repetition or looping is what separates computers from calculators.)
Power Consumption:
-Pdynamic = 1/2*CVDD**2f; Voltage on the capacitor switches at frequency f, it charges the capacitor f/2 times and discharges it f/2 times per second. Discharging does not draw energy from the power supply.
-Pstatic = IDD*VDD
Logic Gates:
-NOT Gate, Buffer, AND Gate, OR Gate, XOR, NAND, NOR, Transmission Gate
Combinational Logic:
characterized by its propagation delay and contamination delay. The propagation delay, tpd, is the maximum time from when an input changes until the output or outputs reach their final value. The contamination delay, tcd, is the minimum time from when an input changes until any output starts to changes its value.
Combinational logic has no cyclic paths and no races. If inputs are applied to combinational logic, the outputs will always settle to the correct value within a propagation delay.
-Building blocks:
full adders, seven-segment display decoders, multiplexer, decoder, priority circuits, arithmetic circuits
-Boolean algebra
-Karnaugh maps: works well for problems with up to four variables. More importantly they give insight into manipulating Boolean equations. Gray code. Dont care for output can be treateed as either 0's or 1's at the designer's discretion.
-Glitches: insight from Karnaugh maps
Sequential Logic:
SR Latch:
D Latch: copies D to Q when clk is 1
D flip-flop: copies D to Q on the rising edge of the clock, and remembers it's state at all other times
synchronous sequential circuit composition teaches us that a circuit is a synchronous sequential circuit if it consists of interconnected circuit elements such that:
-Every circuit element is either a register or a combinational circuit
-At least one circuit element is a register
-All registers receive the same clock signal
-Every cyclic path contains at least one register
-Building blocks:
arithmetic circuits, counters, shift registers, memory arrays, and logic arrays.
Finite state machine:
-An FSM consists of two blocks of combinational logic, next state logic and output logic, and a register that stores the state.
-There are two general classes of finite state machines: Moore machines (the outputs depend only on the current state of the machine), and Mealy machines (the outputs depend only on both the current state and the current inputs).
-HDL descriptions of state machines are correspondingly divided into three parts to model the state register, the next state logic, and the output logic.
Verilog Blocking and Nonblocking Assignement:
-Use always @ (posedge clk) and nonblocking assignments to model synchronous sequential logic.
always @ (posedge clk)
begin
n1 <= d; //nonblocking
q <= n1; //nonblocking
end
-Use continous assignments to model simple combinational logic.
assign y = s ? d1 : d0;
-Use always @ (*) and blocking assignments to model more complicated combinational logic where the always statement is helpful
(A case statement implies combinational logic if all possible input combinations are defined; otherwise it implies sequential logic, because the output will keep its old value in the undefined cases.)
(If statement implies combinational logic, if all possible inputs combinations are handled; otherwise it produces sequential logic.)
(It is good practice to use blocking assignments for combinational logic and nonblocking assignments for sequential logic.)
(Signals in always statement and initial statement must be declared as reg type)
(Not that signal must be declared as reg because it appears on the left hand side of a <= or = sign in an always statement. Nevertheless, it does not mean it's the output of a register, and it can be the output of a combinational logic.)
always @ (*)
begin
p = a^ b; //blocking
g = a & b;//blocking
s = p ^ cin;
cout = g | (p & cin);
end
-Do not make assignments to the same signal in more than one always statement or continuous assignment
-assign statemns must be used outside always statements and are also evaluated concurrently. a type of continuous assignment.
-case statement and if statements must appear inside always statements.
Verilog
-verilog provide generate statements to produce a variable amount of hardware depending on the value of a parameter. generate supports for loops and if statements to determine how many of what types of hardware to produce.
-The
initial statement executes the statements in its body at the start of simulation. initial statements should be used only in testbenches for simulation, not in modules intended to be synthesized into actual hardware. Hardware has no way of magically executing a sequence of special steps when it is first turned on. Like signals in always statements,
signals in initial statements must be declared to be reg.
-Testbenches use the === and !=== operators for comparisons of equality and inequality respectively, because these operators work correctly with operands that
could be x or z.
-the For loop, can be either synthesizable, where it is used to simply expand replicated logic, and they do not loop like in a c program; it can also be non synthesizable, behave like a c program, can have delay in side, not in always statement?.
-Understand the following:
1)
reg and wire (Berkeley CS150)
reg is a confusing term, it is used for anything that holds data. wire cannot retain any data, henceforth it must be driven by continuous assignments.
read 2) to understand what is state.
wire: continuous assignment only, can resolve multiple driver.
reg: a language failure, it's just a varialbe, nothing to do with register. can hold varaible, therefore procedural assignment. cannot be multiple driver. can model both combinational and sequential logic.
2)
Inferred Latch (stackoverflow)
3) blocking and non-blocking
4)
a neat blinky 5) port connection data types wire or reg: (refer to Verilog HDL by Samire Palnitkar)
port as internal unit and external input.
any side that is the data source, it can be either types. (external inputs, or internal outputs)
any side that is the data monitor, it must be net type so can be continuously assigned. (internal inputs, inout, or external outputs). a module instantiation is to connect the input/output signals continuously. so the internal input must be net, and the external output must be net, as it is implicitly driven continuously.
