Hack DUT: Systemverilog Notes

Gotcha: The Behavior of Foreach Loop Variables Depends on How the Array Dimensions Are Specified
How is for-loop synthesizable in any HDL (Verilog)? How is it implemented in hardware?
Solvnet Synopsys ETHERNET SVT UVM main page (also read the FAQ pdf, it's very detailed)
Solvnet Synopsys Ethernet VIP Interface Reference
Systemverilog process class: The process::self() function returns a handle to the current process, that is, a handle to the process making the call. SystemVerilog: Fine grain process control
the repeat loop, expression is evaluated only once at the beginning, other loops, expression is re-evaluated in every iteration: loop evaluation, nandland for loop
verilog generate: nandland generate example
Virtual Class and upcasting

A net represent connections between hardware elements. Just as in real circuits, nets have values continuously driven on them by the outputs of devices that they are connected to.
can only be driven with a continuous assignment statement
a net is the only construct that resolves the effect of different states and strengths simultaneously driving the same signal.
the behavior of a net is defined by a built-in resolution function using the values and strengths of all the drivers on a net. Every time there is a change on one of the drivers, the function is called to produce a resolved value. The function is create at elaboration (before simulation starts) and is based on the kind of net type, wand, wor, tril, etc.

can be driven by continuous assignments, gates, and modules, in addition to being a variables.
can be used anywhere a net is used, except that a logic variable cannot be driven by multiple structural drivers (such as when you are modeling a bidirectional buss)

class based testbenches cannot have continuous assignments because classes are dynamically created objects and are not allowed to have structural constructs like continuous assignments.
Although a class can read the resolved value of nets, it can only make procedural assignments to variables. Therefore, the testbench needs to create a variable that is continuously assigned to a wire (if you want to have multiple drives to that wire).
procedural assignments to variables use the simple rule: last write wins. You are not allowed to make procedural assignemtns to nets because there is no way to represent how the value you assigning should be resolved with the other drivers.

Another form of procedural continuous assignment is provided by the force and release procedural statements. These statements have a similar effect to the assign - deassign pair, but a force can be applied to nets as well as to variables.
A force statement to a variable shall override a procedural assignment, continuous assignment or an assign procedural continuous assignment to the variable until a release procedural statement is executed on the variable.
A force procedural statement on a net shall override all drivers of the net—gate outputs, module outputs, and continuous assignments—until a release procedural statement is executed on the net. When released, the net shall immediately be assigned the value determined by the drivers of the net.

if your testbench drives an asynchronous signal in an interface with a procedural assignment, the signal must be a logic type. Signals in a clocking block are always synchronous and can be declared as logic or wire(?).
wire can resolve multiple structural drivers, but logic cannot. choose depending on your user scenarios.

initial_construct ::= initial statement_or_null
always_construct ::= always_keyword statement
always_keyword ::= always | always_comb | always_latch | always_ff
final_construct ::= final function_statement
function_declaration ::= function [ lifetime ] function_body_declaration
task_declaration ::= task [ lifetime ] task_body_declaration
In addition to these structured procedures, SystemVerilog contains other procedural contexts, such as coverage point expressions, assertion sequence match items, and action blocks.

Binding is like secretly instantiating a module/interface within another RTL file without disturbing the existing code. The binded module/interface is instantiated directly into the target module. How to bind inner signals from DUT?

The singleton pattern is implemented by creating a class wit a method that creates a new instance of the class if one does not exist. If an instance already exists, it simply returns a handle to that object. To make sure that he object cannot be instantiated any other way, you must make the constructor protected. Don't make it local, because an extend class might need to access the constructor.

Rules for expression types (from LRM). The following are the rules for determining the resulting type of an expression:

— Expression type depends only on the operands. It does not depend on the left-hand side (if any).
— Decimal numbers are signed.
— Based numbers are unsigned, except where the s notation is used in the base specifier (as in 4'sd12 ).
— Bit-select results are unsigned, regardless of the operands.
— Part-select results are unsigned, regardless of the operands even if the part-select specifies the entire vector.

— Concatenate results are unsigned, regardless of the operands.
— Comparison and reduction operator results are unsigned, regardless of the operands.
— Reals converted to integers by type coercion are signed
— The sign and size of any self-determined operand are determined by the operand itself and independent of the remainder of the expression.
— For non-self-determined operands, the following rules apply:
— If any operand is real, the result is real.
— If any operand is unsigned, the result is unsigned, regardless of the operator.
— If all operands are signed, the result will be signed, regardless of operator, except when specified otherwise.

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