Ctags and Vim to Work with Systemverilog

refer to the following links, I am just adding some corrections to the original post:
https://coderwall.com/p/fy7stg/vim-and-systemverilog
and this link:
http://kaushalmodi.github.io/2014/03/09/ctags-verilog-and-emacs/

Below is the simplified content of .ctags file for systemverilog (removing variables matching).


--langdef=systemverilog --langmap=systemverilog:.sv.svh.svi
--regex-systemverilog=/^[ \t]*(virtual)?[ \t]*class[ \t]*([a-zA-Z_0-9]+)/\2/c,class/
--regex-systemverilog=/^[ \t]*(virtual)?[ \t]*task[ \t]*.*::([a-zA-Z_0-9]+)[\t]*[(;]/\2/t,task/
--regex-systemverilog=/^[ \t]*(virtual)?[ \t]*function[ \t]*.*::([a-zA-Z_0-9]+)[ \t]*[(;]/\2/f,function/
--regex-systemverilog=/^[ \t]*module[ \t]*([a-zA-Z_0-9]+)/\1/m,module/
--regex-systemverilog=/^[ \t]*program[ \t]*([a-zA-Z_0-9]+)/\1/p,program/
--regex-systemverilog=/^[ \t]*interface[ \t]*([a-zA-Z_0-9]+)/\1/i,interface/
--regex-systemverilog=/^[ \t]*typedef[ \t]+.*[ \t]+([a-zA-Z_0-9]+)[ \t]*;/\1/e,typedef/
--regex-systemverilog=/^[ \t]*`define[ \t]*([a-zA-Z_0-9]+)/`\1/d,define/
--regex-systemverilog=/^[ \t]*`SVT_REPLACEABLE_DEFINE\([ \t]*([a-zA-Z_0-9]+),.*\)/`\1/d,define/
--systemverilog-kinds=+ctfmpied

Steps to gen tags file:
1. do one-time parsing of UVM library (or any dirctories that does not change):
%cd my_UVM_path
%ctags --languages=systemverilog -R .
%mv tags ~/.vim/tags/UVM
2. to use the ctags for you UVM project, add the following to your vimrc file:
set tags=./tags
set tags+=~/.vim/tags/UVM
3. now generate the tags file for the project:
%cd my_project
%ctags -R .


a tips to parse sv files:
%find . -name "*.sv" -o -name "*.svh" | ctags -L -
"-L -" means ctags will get a list of files from STDIN, in this case, from pipes in shell.

ctags shortcut in vimrc:

nnoremap    <M-[>    <C-T>

nnoremap    <M-]>    g<C-]>

#g<C-]> will jump to the tag if there's only one match and will present a list if there are multiple matches.